When plural chips are connected in parallel to an external bus, like in a DRAM (Dynamic Random Access Memory), a signal is often reflected by a chip of which output buffer is in a high-impedance state (Hi-Z). When the signal reflection occurs like this, the quality of the signal on the external bus is degraded. Therefore, when a semiconductor device requiring a high data transfer rate, such as a DDR2 SDRAM (Synchronous DRAM), often includes the ODT function that makes the output circuit as a terminal resistor (Japanese Patent Application Laid-open No. 2003-133943).
When the semiconductor device includes the ODT function, the terminal resistor is not necessary on the mother board. Therefore, the number of parts can be decreased, and the reflection of the signal can be prevented effectively. Consequently, the quality of the signal on the external bus can be increased.
In the DDR2 SDRAM, the ODT is functioned when other chip connected to the same bus is carrying the read operation or the write operation, and the ODT is not functioned during other periods. However, when the data transfer rate becomes very high, the signal quality decreases due to the signal reflection that occurs on the chip itself during the write operation. To solve this problem, it is effective to dynamically change over between the ODT impedances between the period when other chip carries out the read operation or the write operation and the period when the chip concerned carries out the write operation.
However, when the ODT impedance can be dynamically changed, the number of circuit stages between a synchronizing circuit that controls the operation timing of a driver circuit and a data input-output terminal increases. This has a problem of the increase in the inherent delay of a DLL (Delayed Lock Loop). The inherent delay of the DLL is a delay amount between the original clock to be synchronized and the clock synchronized with the original clock. An ideal inherent delay of the DLL is one clock. When the number of circuit stages between the synchronizing circuit and the data input-output terminal is large, the inherent delay of the DLL becomes large, therefore, will be subject to the influence of noise.
Moreover, when the ODT impedance can be dynamically changed, the number of circuit stages between the synchronizing circuit and the data input-output terminal may become larger in the ODT path than in the read path. In this case, there arises a problem that the data output timing or in the ODT execution timing can be easily deviated.
Particularly, when a driver circuit for data output and a driver circuit for the ODT are shared, the number of circuit stages between the synchronizing circuit and the data input-output terminal further increases. Therefore, the above problem becomes more serious.